1. Field of the Invention
The present invention relates to a pattern layout creation method, a program product, and a semiconductor device manufacturing method.
2. Description of the Related Art
Downsizing of semiconductor integrated circuits greatly depends on a lithography technique. Therefore, it is generally difficult to form a device pattern having a width narrower than a lithography resolution limit. To solve such a problem, there are double patterning techniques, as a method of forming a dense device pattern exceeding a lithography resolution performance. As one of the double patterning techniques, there is a technique of forming a very fine pitch pattern on a semiconductor substrate that will otherwise be impossible to form through a single exposure by splitting one-layered photomask of an LSI pattern that has been exposed at once in a conventional photolithography process into two photomasks, and performing the exposure in twice in this state (see, for example, Japanese Patent Application Laid-open No. 2008-261922).
Meanwhile, generally, various conditions such as an exposure amount and a focal position relating to a lithography process are fluctuated, a finished shape is changed. Accordingly, to have a difference between a design pattern shape and an actually obtained pattern shape into a permissive range, it has been required to form a pattern layout that is insensitive to fluctuations of the various conditions, in other words, a pattern layout having a larger process tolerance (a process margin).
However, splitting has been conventionally performed without any regard to the process margin. Thus, there is a problem that sometimes there remains a part in which the process margin is insufficient in the split pattern layout. When there is a part in which the process margin is insufficient in a pattern layout diagram, a finished shape of that part greatly changes depending on fluctuations in various conditions. Thus, there arises a problem that it is not possible to form a highly accurate pattern.